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| ARTICLE |
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| Year : 2009 | Volume
: 55
| Issue : 5 | Page : 218-221 |
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Effects of Dielectric Constant Mismatch on Capacitance-voltage Curve
Ling-Feng Mao
School of Electronics and Information Engineering, Soochow University, 178 Gan-jiang East Road, Suzhou - 215 021, China
| Date of Web Publication | 5-Nov-2009 |
Correspondence Address:
Ling-Feng Mao
School of Electronics and Information Engineering, Soochow University, 178 Gan-jiang East Road, Suzhou - 215 021
China
 DOI: 10.4103/0377-2063.57599
 Abstract | | |
This paper investigates the effects of a dielectric-constant mismatch between gate dielectric and silicon substrate on the capacitance-voltage curve of high-K MOS structures, numerically, via fully self-consistent solutions of Schrφdinger and Poisson equations. Results demonstrate that the capacitance-voltage curve of a high-K MOS structure compared to that of SiO 2 MOS structure with the same equivalent oxide thickness shifts to lower gate voltage with increasing dielectric constant of the gate dielectric, thickness of gate dielectric, and acceptor density in silicon substrate. The results also demonstrate that a higher dielectric thickness, thicker gate dielectric, and higher acceptor density for a high-K MOS structure lead to a larger increase in capacitance compared to SiO 2 MOS structure with the same equivalent oxide thickness. Keywords: Capacitance, High-K gate dielectric, Inversion, Metal-oxide-semiconductor field effect transistor.
How to cite this article:
Mao LF. Effects of Dielectric Constant Mismatch on Capacitance-voltage Curve. IETE J Res 2009;55:218-21 |
| 1.Introduction | |  |
SiO 2 is a key component of MOS (metal-oxide semi conductor) structure, solar cells and optical fibers. Continuing with the application of device scaling, MOS device technology has evolved to a stage where device performance would approach its physical limit. It is most likely that SiO 2 will fail to meet industry requirement of an insulating barrier due to the defect-assisted leakage current and quantum-mechanical tunneling current. High-permittivity (high-K) gate dielectrics are seen as potential solutions for low leakage technologies as these materials allow for physically thicker films with small electrical thickness. The high-K materials that could potentially replace SiO 2 include Ta 2 O 5 , TiO 2 , Y 2 O 3 , CeO 2 , SrTiO 3 , Zr-Sn-Ti-O, Al 2 O 3 , La 2 O 3 , HfO 2 , and ZrO 2 . Related research has been rapidly increasing [1],[2],[3],[4],[5],[6] .
The effect of the effective electron mass mismatch in an MOS structure on the quantization has been reported [7] . It can also be used to explain temperature dependence of gate leakage current [8] and injection channel electron velocity on the gate leakage current [9] . Just like electron mass mismatch, the dielectric-constant mismatch between silicon and gate dielectric has not been thoroughly investigated.
A field effect transistor is a capacitance-operated device in which the source-drain current of the field effect transistor depends on capacitance. To understand scaling limits and ensure that the selected high-K materials are highly scalable and usable for many future generations of technology, it is necessary to discuss the impact of dielectric-constant mismatch on the capacitance of a high-K MOS structure when the equivalent oxide thickness is kept same.
| 2.Method | | |
The capacitance of MOS structure generally consists of three components in series connection [10],[11] : The per unit area gate dielectric capacitance (C ox = ε0 /t ox), depleted poly-gate capacitance (CGD ), and surface capacitance (CSB ). The total capacitance C is thus given by [10],[11]
In surface depletion and inversion regimes, surface capaci tance (CSB ) results from the depletion charge and induced electron charge. Quantum confinement in the inversion layer affects capacitance primarily via surface capacitance [11] . In the calculation of capacitance, it is obtained as a derivative of the total sheet charge density in Si substrate with respect to the bias voltage (C = d Q/d V). Frequency, sensitive of space charge, has not been considered in this work. Static capacitance has been calculated.
One-dimensional Schrodinger equation under the parabolic band approximation can be written as
Where, tunnelling direction z is perpendicular to the Si/ SiO 2 interface, φ(z) represents the potential energy along the z direction, mz and pz denote the mass and momentum operators perpendicular to the Si/gate oxide interface respectively, and E is the electron energy.
In general, the 1-D Poisson equation along the z direction for a MOS structure can be written as
Where, φ(z) is the electrostatic potential, (z) is spatially dependent dielectric constant,  are the ionized donor and acceptor concentrations respectively, and n (z) and p (z) are the electron and hole densities, respectively. An accurate description of inversion electrons of MOS structure required a self-consistent solution to Poisson and Schrodinger equation. In this paper, examples 2 and 3 have been self-consistently solved with the finite-difference method [12] to study the effects of dielectric constant mismatch on the capacitance of MOS structures with the maximum allowed correction, in eV, to the band diagram for the converged structure of 1 x 10-10 eV.
| 3.Results and Discussion | | |
For the electrical design of MOS structure (the band structure is shown in [Figure 1]), it is convenient to define an 'electrical thickness' of high-K gate dielectric in terms of its equivalent silicon dioxide thickness or 'equivalent oxide thickness' (EOT) as
where  are the static dielectric constant and thickness of SiO 2 layer, respectively. K and thik are the relative permittivity and thickness of high-K dielectric layer, respectively.
HfO 2 and ZrO 2 are very promising candidates among the high-K alternatives. According to Ref. [1] , the relative dielectric constants of HfO 2 and ZrO 2 range from 16 to 30 and from 12 to 16, respectively. The conduction band offset of HfO 2 is 1.5 eV and bandgap of HfO 2 ranges from. 4.5 to 6.0 eV, whereas the conduction band offset of ZrO 2 ranges from 1.4 to 1.5 eV and bandgap of ZrO 2 ranges from 5.7 to 5.8 eV. Additionally, the relative dielectric constant of ZrSiO 4 ranges from 10 to 12, the conduction band offset is 1.5 eV, and bandgap of ZrSiO 4 is ~6.0 eV; about 0.20 m0 is used for both HfO 2 and ZrO 2 [2] . Thus it is possible to fabricate high-K MOS structure when the dielectric constant is changed but the effective electron mass and barrier height keep almost constant. We have chosen an effective electron mass of 0.2 m0 , a band gap of 5.8 eV, and the conduction band offset of 1.5 eV of dielectric in a high-K MOS structure with a metal gate and the silicon substrate thickness of 500 nm. The effective electron mass of 0.5 m0 , band gap of 9.0 eV, and conduction band offset of 3.15 eV for SiO 2 have been chosen according to Ref. [1] . An average effective electron mass 0.26 m 0 of silicon is used. The coupled Schrodinger-Poisson equations are self-consistently solved in the region from the metal/gate dielectric interface to the position in the silicon substrate that is 300 Å away, whereas Boltzmann statistics is used outside the region.
[Figure 2] depicts the calculated capacitance-voltage curves of MOS structure under inversion bias. This Figure clearly demonstrates that a higher dielectric constant mismatch between the gate dielectric and silicon substrate results that the capacitance-voltage curve shifts to a lower gate voltage. This Figure also clearly demonstrates that a high-K MOS structure with a higher dielectric constant has a larger increase in capacitance compared to a SiO 2 MOS structure when the EOT is same. Basically, it is because such a mismatch can affect on the quantization of the inversion layer . The total capacitance is thus changed because surface capacitance is affected by the quantum effect [11] .
[Figure 3]a shows how the thickness of gate dielectric affects on the capacitance ratio of a high-K MOS structure to that of a SiO 2 MOS structure with the same EOT. [Figure 3]a illustrates that the capacitance-voltage shifts to lower gate voltage with increased thickness of dielectric. [Figure 3]a also clearly demonstrates that a thicker gate dielectric has a larger increase in the capacitance compared to a conventional MOS structure with the same EOT. [Figure 3]b illustrates how the acceptor density affects on the capacitance ratio of a high-K MOS structure to that of a SiO 2 MOS structure with the same EOT. [Figure 3]b shows that the capacitance-voltage curve shifts to lower gate voltage with increased acceptor concentration. [Figure 3]b also demonstrates that a higher acceptor density has a larger increase in the capacitance compared to a SiO 2 MOS structure with the same EOT.
3.1 Physical Explanation of Shift of Capacitance-voltage Curve
The electric field at the interface (gate oxide/silicon substrate) within silicon substrate determines quantization in the inversion layer. If this electric field keeps constant, quantization, inversion does not change. Hence, results on energy quantization are not needed.
 if the interface is free of electric charge, where Esi-in and EGO are the electric field at the silicon substrate and gate oxide sides of the silicon substrate/gate oxide interface, respectively, K and ε si are the relative permittivity of gate oxide and silicon substrate, respectively. Obviously, a higher gate voltage for high-K gate oxide is needed for the same electric filed at the silicon substrate side of the silicon substrate/gate oxide interface compared to that for a SiO 2 case. This also implies a higher gate voltage for high-K gate oxide for the same energy quantization compared to that for SiO 2 . It is well known that energy quantization decreases the carrier density of the inversion layer. This means that the introduction of high-K gate oxide will decrease the quantum mechanical effects. It represents that there will larger charge density in the inversion layer of a high-K MOS structure compared that in a SiO 2 MOS structure at the same gate voltage. According to C = dQ/dV, the capacitance of a high-K MOS structure will be larger than that of a SiO 2 MOS structure at the same gate voltage.
On the basis of the above analysis, the physical origin of the shift in [Figure 2] and [Figure 3] can be obtained. Another important factor is change in the barrier height between high-K gate oxide and silicon, which results in a change in energy quantization. Both will have an effect on the capacitance-voltage curve. It is possible to fabricate high-K MOS structure when the dielectric constant is changed but the effective electron mass and barrier height keep almost constant and a change in dielectric constant will be more important.
| 4.Conclusions | | |
The effects of dielectric constant mismatch between the gate dielectric and silicon substrate have been investigated via a self-consistent solution to the coupled Schrφdinger-Poisson equations. Results illustrate that a higher dielectric constant mismatch in a high-K MOS structure leads to shift in capacitance-voltage curve to a lower gate voltage compared to a SiO 2 MOS structure with the same EOT when the dielectric constant of gate dielectric, thickness of gate dielectric and acceptor density increase. At the same time, the most affected regions in the capacitance-voltage curve increase with the increased dielectric constant of gate dielectric, thickness of gate dielectric and acceptor density.
| 5.Acknowledgment | | |
The author acknowledges financial support from the National Natural Science Foundation of China under Grant 60606016. This work was partly supported by the Natural Science Foundation of the Jiangsu Higher Education Institutions of China (Grant No. : 06KJD510158 ).
| Authors | | |
 Ling-Feng Mao received his Ph.D. degree in microelectronics and solid State Electronics from the Peking University, Beijing, P. R. China, in 2001. He is a professor in the school of electronics& information engineering, Soochow University, P. R. China. His research activities include modeling and characterization of semiconductors and semiconductor devices, and characterization of quantum devices, the fabrication and modeling of integrated optic devices and microwave devices.
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[Figure 1], [Figure 2], [Figure 3]
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