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| ARTICLE |
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| Year : 2009 | Volume
: 55
| Issue : 6 | Page : 309-314 |
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A 1.5 V, 0.85-13.35 GHZ MMIC Low Noise Amplifier Design Using Optimization Technique
Arjuna Marzuki1, Ali Yeon Md. Shakaff2, Zaliman Sauli3
1 School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia
2 School of Computer Engineering, University Malaysia Perlis, Complex UniMAP, Jejawi, Perlis - 02600, Malaysia
3 School of Microelectronic Engineering, University Malaysia Perlis, Complex UniMAP, Jejawi, Perlis - 02600, Malaysia
| Date of Web Publication | 18-Jan-2010 |
Correspondence Address:
Arjuna Marzuki
School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang
Malaysia
 DOI: 10.4103/0377-2063.59172
 Abstract | | |
This paper describes how a broadband, 1.5 V, 0.85 - 13.35 GHz low noise amplifier in 0.15 mm 85 GHz PHEMT process is synthesized to simultaneously meet multiple design specifications such as bandwidth, noise f0 igure, power gain and power consumption. Power-constrained synthesis technique is used to design the broadband amplifier. The simulated peak S21 is 19.8 dB, maximum noise Figure is 2.5 dB, 3-dB bandwidth is 12.5 GHz and power consumption is 73.5 mW. The calculated Figure of merit (FOM) is better than many reported broadband low noise amplifier (LNA). Keywords: Broadband amplifier, Integrated circuit, Monolithic microwave integrated circuit, optimization, pseudomorphic high electron mobility transistor, power-constrained.
How to cite this article:
Marzuki A, Md. Shakaff AY, Sauli Z. A 1.5 V, 0.85-13.35 GHZ MMIC Low Noise Amplifier Design Using Optimization Technique. IETE J Res 2009;55:309-14 |
| 1.Introduction | |  |
A broadband amplifier is in demand for broadband wireless applications such as ultra wideband application [1] . The broadband amplifier can also be applied to multiple-band applications such as personal communication service (PCS), international mobile telecomunication-2000 (IMT-2000) and wireless local area network (WLAN) [2] .
There are many types of broadband topology or architecture that can be applied for the design. Parallel architecture, which employs many dedicated signals together with band pass filters and narrow band low noise amplifiers (LNAs), is popular for broadband. However, this topology leads to bigger die size. Distributed amplifier topology can be used for the design but it also increases die size and has poor performance for LNA. A cascode topology with wideband matching which can also be used consumes die area. Other than larger die size these topologies are prone to oscillation.
Common source amplifier with resistor and capacitor (RC) feedback from drain to gate would provide a good solution for broadband application. This topology can offer stability and therefore reduce any possibility of oscillation. The drawback of this topology is undoubtedly high noise.
Most of these broadband amplifiers employ noise cancellation technique [3] . This technique uses auxiliary amplifier as a feedback to reduce the noise which increases the die size. Low noise technology such as pseudomorphic high electron mobility transistor (PHEMT) can instead be used in the design. The PHEMT technology is cheaper solution for low volume market segment. Hence, RC feedback topology is chosen as the topology of the broadband amplifier. The process technology of 0.15 mm, 85 GHz PHEMT is used for this work.
Simulation-based optimization technique is used to design the amplifier. This technique will reduce the number of design cycles. Agilent ADS software is employed for the optimization.
Target specification for the amplifier is power gain, S21 = 18 dB, noise Figure, NF = 3 dB, bandwidth = 12 GHz and power consumption is 70 mW. The amplifier must be stable at all frequencies. This paper is in four sections: This section introduces the challenges and the decision to use RC feedback. The cascade RC feedback amplifier section explains the set up of the optimization. This section also explains the cascade RC feedback amplifier. The third section includes results and discussion on observations. Finally, the conclusion is in the last section of this paper.
1.1 Basic Theory of Cascade Resistor and Capacitor Feedback Amplifier
[Figure 1] shows the RC feedback amplifier schematic which consists of two stages of RC feedback amplifiers. The unit gate width (UGW) of M1 and M2 is 50 mm.
RIN, CIN, ROUT, COUT, ROUT2, COUT2 are primarily used to stabilize the circuit. These components value will be finalized during the optimization. RS, CS, RS2, CS2 and RIN2 are used to bias M1 and M2. This configuration must ensure voltage at gate M1 and M2 is 0 V. To define RS and RS2, usually a current value must be decided first. One can calculate the value of these resistors using the Ids vs. Vgs curve [Figure 2], CS and CS2 are used as bypass capacitors so that AC gm will be equal to DC gm. In other words, these capacitors will short the source of the transistors to the ground, the value of reactance of this capacitor must be small at the interested frequency range. RFB, CFB, LFB and RFB2, CFB2 are used as feedback networks for M1 and M2 respectively. These components can, undoubtedly, affect performance of the whole circuit. It can affect the gain, input and output return loss. CCC is coupling capacitor. L, CC, RS, RL are external components with RS and RL equal to 50 V, CC equal to 100 pF and L equal to 0.1 μH. The core circuit of single-stage closed-loop gain, AV
where GF, GS, AOL is conductance of feedback resistance, conductance of source resistance and open-loop gain respectively. The closed-loop gain will be equal to an open-loop gain if GF approaches zero. In this case, the open loop gain is referring to transistor gain without feedback topology.
1.2 Implementation of Simulation-Based Optimization
Core-based design with parasitic-aware approach Marzuki et al., [4] was used in designing the monolithic microwave integrated circuit (MMIC). The flow is shown in [Figure 3]. This paper presents the activity in step circuit optimization.
To reduce input port sensitivity with respect to the load, transistor size must be determined. [Figure 4] and [Figure 5] are simulated result using transistors measurement-based model with standard s-parameter test bench as shown in [Figure 6]. [Figure 4] shows the range of transistor finger for S12 <-20 dB. Low S12 could reduce the sensitivity [5] .
[Figure 5] shows S21 of transistor with different finger values. As discussed in the previous section, the required power gain of the amplifier is 18 dB. Hence, it is decided to choose device finger which can deliver minimum gain of 14 dB through out the operating frequency.
From [Figure 4] and [Figure 5], it is clear that finger value from 2 to 10 is chosen for optimization. [Table 1] shows the design variables which will be optimized in order to achieve the required specifications. These design variables are the same for power-constrained and non-power-constrained. The current budget is 50 mA for the power constrained while no current budget for non-power-constrained.
| 2.Results and Discussion | | |
[Table 2] shows the optimized design variable of ideal components. The current consumption for non-power-constrained is 60 mA. Optimization with gradient type is used for all conditions. These ideacomponents are replaced with measurement-based modeled component from foundry. Self-resonant frequency for all passive components is higher than 14 GHZ.
[Figure 7], [Figure 8] and [Figure 9] show final the simulated results of modelled components from foundry. The 3-dB bandwidth of 12.5 GHz is shown in [Figure 7].
[Figure 8] shows noise Figure vs. frequency. Maximum noise Figure is 2.5 dB. The broadband amplifier is unconditionally stable; this is shown in [Figure 9]. The mu_load and mu_source are more than 1.
Monte-Carlo analysis is done for Noise Figure and S21. The analysis is done with standard deviation of 2 for RS, RS2, RFB and RFB2. The results are shown in [Figure 10] and [Figure 11]. Both results show that the parameters are still within the specification.
[Table 3] summarizes most of broadband amplifier works. Amplifiers are often compared using Figure of merit (FOM) Linten et al. [6] , the better the FOM the better is the design. The formula of FOM is shown in equation (2).
The works [7],[8],[9],[10] do not use any simulation-based optimization technique and non-power constrained designs. These are more on ways to meet the bandwidth requirement. Work [1],[12] use current as one of the constraints for the broadband amplifier design, but there are no reports on the performance of these works on non-power-constrained.
This work has shown that power constraint is important to get better performance for broadband amplifier; this can be seen from the FOM of power-constrained is 0.4 better than non-power constrained. The layout [Figure 12] is manually drawn and die size is 1.162 mm 2 . One typical GaAs wafer price is approximately USD 4,000. Therefore the die cost for 6 inch wafer is approximately 25 cents. The design is targeted to be tested using standard microwave on-wafer measurement method, thus there is no study on the design performance due to package parasitic. The layout uses back via process which eliminates the ground pad.
| 3.Conclusion | | |
Amplifier with performance of 12.5 GHz for 3dB-bandwidth, 73.5 mW of power consumption, a noise Figure of 2.5 dB and power gain of 19.8 dB is designed and fabricated. A simulation-based optimization technique is used to design the broadband amplifier. For this work, common source with resistor and capacitor feedback from drain to gate has been employed. Two amplifiers are arranged in cascade to achieve sufficient power gain, sensitivity of the transistor size reviewed and investigated. This step has been introduced to broadband amplifier design methodology. It is clear that for RC feedback, topology, power constraint and design technique would give better performance. Since the mask cost for GaAs is less than the RF CMOS, this work offers a good bargain for a commercialized product.
| Author | | |
 Arjuna Marzuki received B.Eng. in electronics from University of Sheffield, UK in 1997 and MSc from Univ. Sains Malaysia in 2004. After graduating with his first degree, he joined Hewlett-Packard as RFIC Design engineer. Currently he is a lecturer in Universiti Sains Malaysia.
 Ali Yeon Md. Shakaff recieved his Ph.D. in Electronic Engineering from the University of Newcastle-upon-Tyne, England in 1987. Currently he is a Professor in Universiti Malaysia Perlis. His current research interests are in Embedded Systems Design and Sensors.
 Zaliman Sauli is an associate professor in Universiti Malaysia Perlis. He was dean of School of microelectronic in Unimap for several years. His current research interests are in microelectronic.
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[Figure 1], [Figure 2], [Figure 3], [Figure 4], [Figure 5], [Figure 6], [Figure 7], [Figure 8], [Figure 9], [Figure 10], [Figure 11], [Figure 12]
[Table 1], [Table 2], [Table 3]
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