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| ARTICLE |
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| Year : 2011 | Volume
: 57
| Issue : 5 | Page : 407-412 |
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A Novel Approach to the Design of MESFET-based MMIC Switches Using Common-gate Parameter Extraction
Rajesh Kumar Prabakaran, Ananjan Basu, Shiban K Koul
Centre for Applied Research in Electronics, Indian Institute of Technology Delhi, New Delhi, India
| Date of Web Publication | 24-Nov-2011 |
Correspondence Address:
Rajesh Kumar Prabakaran
Centre for Applied Research in Electronics, Indian Institute of Technology Delhi, New Delhi
India
 DOI: 10.4103/0377-2063.90149
 Abstract | | |
This paper describes a new approach to the Single-pole Double-throw (SPDT) switch design using MESFETs. The device models were extracted from measured data for a number of FETs, and verified in the frequency band of 1-20 GHz. A switch was designed using these device models, and showed good results in simulation. Keywords: Common-gate, MESFET, MMIC switch, Parameter extraction
How to cite this article:
Prabakaran RK, Basu A, Koul SK. A Novel Approach to the Design of MESFET-based MMIC Switches Using Common-gate Parameter Extraction. IETE J Res 2011;57:407-12 |
| 1. Introduction | |  |
Gallium arsenide (GaAs)-based FET devices (MESFETs/HEMTs) are important switching elements in high-frequency control circuits such as phase shifters, switches, and attenuators. The FET as a passive control device is basically a voltage-controlled resistor whose value is determined by the DC bias applied at the gate of the device. For most control applications, the FET is switched between a low-impedance or conducting state and high-impedance or nonconducting state, corresponding to the saturation and cut-off regions of the FET characteristics, respectively. The FET operates in the ON state at Vgs = 0 and in the OFF state at 
The actual pHEMTs that were used for the design have the gate length of L = 0.5 μm and variable gate widths. Several sophisticated designs have been reported [1],[2],[3] for enhancing the bandwidth and other parameters of MMIC switches, using the "filter-integrated switch" concept. However, these techniques either use very high performance devices [1] or sophisticated circuit design techniques to achieve band-pass [2] or traveling-wave [3] structures. We demonstrate a simple approach to switch design which results in a low-pass structure. Our technique relies on the accurate knowledge of the device model. Since we have focused on FETs which can be fabricated with conventional optical photolithography, our gate length is restricted to 0.5 μm, and we get higher parasitics compared to the devices in ref. [1] . So, in the first section of this paper, the technique used to extract the small signal model of the HEMT is elucidated.
Most of the literature available deals with parameter extraction from the common-source data [4] . This is not good enough in our case, because if the device layout is different while extracting parameters and while fabricating switches, the model used will not be good enough. Some information is available about common-gate parameter extraction [5],[6],[7] , but we have developed a new algorithm which is described in the next section, and it is shown by measurement that the model is indeed very accurate. In section 3, the use of this model for switch design is described.
| 2. HEMT Switch Modeling | | |
2.1 Issues with Modeling
The small signal equivalent circuit of the HEMT as a switch is shown in [Figure 1]. The S parameters of the cold HEMT were measured at gate voltages of 0.25, −2.25, −2.5, and −2.75 V. At the gate voltage of 0.25 V, the HEMT is conducting and at the other three gate voltages, the HEMT is pinched off. The HEMT is to be used as a switch by toggling the gate voltage between 0.25 and −2.5 V.
The extrinsic inductances can be extracted by measuring the S parameters of the HEMT for Vgs = 0 and Vds = 0 [4] , when the device is connected in common-source configuration. In this case, it is seen that the imaginary part of the impedance depends only on the extrinsic inductance.
But when the HEMT is used as a switch, then it is connected in the common-gate configuration. Here the impedance of the device in the ON state depends not only on the inductances but also on the capacitances Cgs and Cgd .
Therefore, all the model parameters have to be extracted by some form of optimization. The parameters that are common between the ON and the OFF states are the extrinsic parameters. Therefore, some form of algorithm is required by which the extrinsic parameters as well as the intrinsic parameters can be determined. The algorithm is as mentioned below.
2.2 Initial Values
The first step of the optimization algorithm is to determine the initial values of the intrinsic parameters. This prevents the algorithm from getting stuck in local minima. The following procedure is implemented:
- Assume the extrinsic parameters to be zero. Therefore, now the circuit that is left is a simple pi network whose Y parameters can be easily determined
- Convert the measured S parameters to Y parameters
- Find the individual circuit elements using the equations below [5] :
The values of the intrinsic parameters are calculated for the lowest frequency point. At that frequency, the values of the impedance due to the bond pad capacitances Cps and Cpd are large and the impedance due to the extrinsic inductances is small. Therefore, it can be safely assumed that the final values of the intrinsic parameters would be close to those determined by the equations above.
2.3 Optimization Algorithm
To extract the model parameters only three S parameter measurements are necessary. Two measurements are for gate voltages below the pinch-off voltage. These are the OFF state voltages and any other voltage below the OFF state. The third measurement is on the ON state gate voltage. In this case, the OFF state gate voltage is −2.5 V and the ON state gate voltage is 0.25 V. The other voltage is −2.75 V. The optimization algorithm is as given below:
- The initial values of the intrinsic parameters at the three gate voltages are calculated and substituted into the three equivalent circuits
- For the circuit with a gate voltage of 0.25 V, the three extrinsic inductances and the intrinsic parameters are taken as the optimization variables. At this voltage, impedance Rds is much smaller than the impedance of Cds . Therefore, Cds can be ignored from the equivalent circuit of [Figure 2]. The S parameters are therefore heavily influenced by the extrinsic inductances. The circuit is then optimized using the gradient optimization algorithm till a reasonably small error value is obtained
- The values are calculated as
where L = new values Ls , Ld , Lg and
L0 = old values of Ls , Ld , Lg . - The inductance values are substituted in all three circuits
- For the circuit with a gate voltage of −2.75 V, the three extrinsic resistances and the intrinsic parameters are taken as the optimization variables. The circuit is then optimized using the gradient optimization algorithm till a reasonably small error value is obtained
- The values are calculated as
where R = new values Rs , Rd , Rg and
R0 = old values of Rs , Rd , Rg . - The resistance values are substituted in all three circuits
- For the circuit with a gate voltage of −2.5 V, the two bond pad capacitances and the intrinsic parameters are taken as the optimization variables. At this voltage, impedance of Cds is much smaller than the impedance of Rds . Therefore, Rds can be ignored from the equivalent circuit of [Figure 2]. The capacitive impedance is much larger than the inductive impedance. Therefore, the S parameters are heavily influenced by the intrinsic capacitance and the bond pad capacitances. The circuit is then optimized using the gradient optimization algorithm till a reasonably small error value is obtained
- The value is calculated as
where C = new values Cps , Cpd and
C0 = old values of Cps , Cpd . - The capacitance values are substituted in all three circuits
- Steps 2-10 till the values of deltaL, deltaR, and deltaC are reasonably small, around 10−4.
2.4 Results
S parameters of HEMT switches were measured to verify the optimization procedure. [Figure 2] and [Figure 3] show matching between the modeled and the measured S parameters for the ON and OFF states of the switch. As can be seen in these figures, the matching is excellent over the entire frequency range.
[Table 1] shows the model parameters extracted at 1 GHz for gate widths of 4 × 100 μm, 6 × 100 μm, and 8 × 100 μm. The table also shows the variation of R ds-on and Cds-off with the gate width. It shows consistent values per micron of the gate width for the channel elements.
| 3. Single-Pole Double-Throw Switch Design | | |
A commonly used distributed topology [8] was adopted for the switch design as shown in [Figure 4]. Our technique extends the operating frequency of the switch by absorbing the OFF state capacitance of shunt-mounted transistors into a low-pass filter in a simple way.
A length of high-impedance transmission line, which represents the series inductance of the filter, separates each shunt transistor. Provided the OFF-state capacitance of the transistors is low enough, a filter can be produced with a cut-off frequency beyond the desired upper operating frequency.
The path from the input to one output is low loss while the path from the input to the other output is high isolation. The shunt-mounted PHEMTs in the ON-case path are pinched off and the corresponding series device is switched on (low-resistance state). Since the parasitic capacitance of the shunt-mounted transistors has been absorbed into a filter structure, the ON-case path loss is low.
The shunt-mounted PHEMTs in the OFF path are switched on and provide a low-impedance path to ground. The corresponding series transistor is pinched off and at low frequencies, it is high impedance. At higher frequencies, the parasitic capacitance means the transistor provides little isolation but the switch is designed so that the line length and the series transistor transform the low impedance of the first shunt-mounted transistor to a high impedance.
3.1 Switch Design
The initial design is done with a SPST configuration. This will be extended to the single-pole double-throw (SPDT) configuration at a later stage. The first step is to determine the number of shunt arms. The more the number of shunt arms, the greater will be the isolation and the chip size. As specifications, we have chosen the following numbers which are fairly realistic: frequency DC to 10 GHz, insertion loss < 2 dB, isolation > 60 dB, return loss > 15 dB. To keep the chip area within reasonable limits, a maximum of five shunt arms can be used. Here the specified isolation of 60 dB can be achieved by connecting four shunt arms as shown in [Figure 5]. The associated performance is shown in [Figure 6]. It is seen in [Figure 6] that the insertion and the return losses are very high. Improving the return losses will contribute to an increase in insertion loss also. The existing lumped element circuit is modified by spacing each of the devices with an inductor (0.2 nH) to obtain a better match. The modified topology and the corresponding performance are shown in [Figure 7] and [Figure 8].  | Figure 6: Insertion loss, isolation, and return loss of the ideal switch design.
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 | Figure 8: The improved performance after the inclusion of interstage matching inductance.
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The performance shown in [Figure 8] is close to the requirement except for the isolation. This can be adjusted in the next step of the design flow - translation to the foundry equivalent models.
The lumped element circuit is first translated by incorporating transmission lines for inductors and replacing the ideal ground elements with ground-via models. [Figure 9] depicts the translated design and its performance. All this was for the standard 0.1-mm-thick GaAs substrate.
To improve the performance, the interstage inductors are optimized. When the SPST switch is connected as a SPDT switch, an improvement of around 5 dB is achieved in the isolation. So after optimization, the minimum optimization should be 55 dB. A small improvement in insertion loss is also obtained. Its performance is shown in [Figure 10]. It is important to note that an accurate model is important; using a simple model and obtaining closed-form expressions from filter-design theory will not work here, because the parasitics are not very small.
As can be seen in [Figure 10], the isolation is well below 60 dB at almost the entire frequency band. Now connecting this SPST switch as two arms of the SPDT switch gives the performance as shown in [Figure 11].
[Figure 11] shows that the isolation is well below 60 dB over the entire frequency band. The insertion loss is below 2 dB and the maximum return loss is −16 dB over the entire frequency band.
| 4. Conclusion | | |
A new optimization technique for the modeling of a HEMT operated in common-gate configuration is proposed. Parameters extracted at 1 GHz were validated for the frequency range of 1-20 GHz with excellent accuracy.
A simple design method for the SPDT switch is also proposed where depending on the isolation and the insertion loss the size of the HEMT is optimized. This simple technique works well because the parameter extraction is accurate.
| References | | |
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| 2. | Z M Tsai, Y S Jiang, J Lee, K Y Lin, and H Wang, "Analysis and Design of Bandpass Single-Pole-Double-Throw FET Filter-Integrated Switches", IEEE Transactions On Microwave Theory And Techniques, Vol. 55, No. 8, Aug. 2007.
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| Authors | | |
 Rajesh Kumar Prabakaran completed M.Tech in RF Design and Technology from C.A.R.E. I.I.T.Delhi in 2006.
 Ananjan Basu was born Aug 12, 1969. He received the B.Tech degree in electrical engineering and M.Tech degree in communication and radar engineering from the Indian Institute of Technology Delhi (I.I.T.DeIhi), in 1991 and 1993 respectively, and the PhD. degree in electrical engineering from University of California at Los Angeles (UCLA), in 1998. He has been with the Centre for Applied Research in Electronics, I.I.T.DeIhi as an Assistant Professor (2000-2005) and Associate Professor (since 2005). His specialization is in microwave and millimetre-wave component design and characterization.
 Shiban K. Koul is a Professor at the Centre for Applied Research in Electronics, Indian Institute of Technology Delhi. His research interests include: RF MEMS, Device modeling, Millimeter wave IC design and Reconfigurable microwave circuits including antennas. He is the Chairman of M/s Astra Microwave Pvt. Ltd, a major private company involved in the Development of RF and Microwave systems in India. He is author/co-author of 195 Research Papers and 7 state-of-the art books. He has successfully completed 25 major sponsored projects, 50 consultancy projects and 33 Technology Development Projects. He holds 7 patents and 4 copyrights.
Dr. Koul is a Fellow of the IEEE, USA, Fellow of the Indian National Academy of Engineering (INAE) India and Fellow of the Institution of Electronics and Telecommunication Engineers (IETE) India, He has received Gold Medal by the Institution of Electrical and Electronics Engineers Calcutta (1977); S.K.Mitra Research Award (1986) from the IETE for the best research paper; Indian National Science Academy (INSA) Young Scientist Award (1986); International Union of Radio Science (URSI) Young Scientist Award (1987); the top Invention Award (1991) of the National Research Development Council for his contributions to the indigenous development of ferrite phase shifter technology; VASVIK Award (1994) for the development of Ka- band components and phase shifters; Ram Lal Wadhwa Gold Medal (1995) from the Institution of Electronics and Communication Engineers (IETE); Academic Excellence award (1998) from Indian Government for his pioneering contributions to phase control modules for Rajendra Radar; and Shri Om Prakash Bhasin Award (2009) in the field of Electronics and Information Technology.
Dr. Koul has recently been appointed as a Distinguished Microwave Lecturer by the IEEE Microwave Theory and Techniques (MTT) Society, USA for the period 2012-2014. He is also a serving AdCom member of the MTT-society.
[Figure 1], [Figure 2], [Figure 3], [Figure 4], [Figure 5], [Figure 6], [Figure 7], [Figure 8], [Figure 9], [Figure 10], [Figure 11]
[Table 1]
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