|
 |
| ARTICLE |
|
|
|
| Year : 2012 | Volume
: 58
| Issue : 3 | Page : 197-204 |
|
|
Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs
Mike Schwarz1, Thomas Holtij1, Alexander Kloes2, Benjamín Iñíguez3
1 Technische Hochschule Mittelhessen, Competence Center for Nanotechnology and Photonics, Wiesenstrasse 14, Giessen 35390, Germany; Universitat Rovira i Virgili, Department d'Enginyeria Electronica, Elèctrica i Automàtica, Avda. Païson Catalans, 26., Campus Sescelades, Tarragona 43007, Spain,
2 Technische Hochschule Mittelhessen, Competence Center for Nanotechnology and Photonics, Wiesenstrasse 14, Giessen 35390, Germany,
3 Universitat Rovira i Virgili, Department d'Enginyeria Electronica, Elèctrica i Automàtica, Avda. Païson Catalans, 26., Campus Sescelades, Tarragona 43007, Spain,
| Date of Web Publication | 16-Jun-2012 |
Correspondence Address:
Mike Schwarz
Technische Hochschule Mittelhessen, Competence Center for Nanotechnology and Photonics, Wiesenstrasse 14, Giessen 35390, Germany; Universitat Rovira i Virgili, Department d'Enginyeria Electronica, Elèctrica i Automàtica, Avda. Païson Catalans, 26., Campus Sescelades, Tarragona 43007, Spain
 DOI: 10.4103/0377-2063.97326
 Abstract | | |
A new technique to calculate the channel electric field in Double-gate MOSFETs and Schottky barrier Double-gate MOSFETs (SB-DG-MOSFETs) in sub-threshold region is presented. 2D Poisson΄s equation is solved in an analytical closed form with the conformal mapping technique. The estimated solution of the two-dimensional electric field with its complex components is analyzed with the bias conditions for accumulation and inversion regions, which have been applied and studied in detail. A comparison with data simulated by 2D TCAD Sentaurus simulator for channel lengths down to 22 nm was made and is in a good agreement to this simulation results. Keywords: Analytical closed-form, Compact modeling, Conformal mapping, Device modeling, Double-gate MOSFET, Electric field, Schottky barrier, 2D Poisson
How to cite this article:
Schwarz M, Holtij T, Kloes A, Iñíguez B. Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs. IETE J Res 2012;58:197-204 |
| 1. Introduction | |  |
Nowadays, research for sub-20 nm devices focuses on new SOI-type structures and downscaling to the sub-10 nm range is possible with so called DG-MOSFETs, FinFET, and (Gate-all-around) GAA FETs. With these alternative device designs on SOI substrate, short channel effects (SCE) are reduced dramatically [1] and an improvement of gate control is observed. The Schottky barrier (SB) MOSFET is one of the promising structures because of its high scalability even down to the sub-10 nm region and good process compatibility with current standard Si technologies as well as its metallic source/drain (S/D) electrodes with low specific resistances [2] . As an essential part, precise compact models of these devices are needed for implementation in circuit simulators and circuit design tools. In multigate devices, these models have taken into account two- or even three-dimensional effects.
The electrical field in the channel region in sub-threshold operation is of great importance for the estimation of the tunneling probability of carriers at the SBs. Tunneling currents below threshold and the ambipolar behavior depend on that electric field. To define a compact model for circuit simulations, an analytical closed-form solution for the electric field at S/D is necessary. In [3] , we presented an analytical closed-form model for the electrostatic potential of a SB Double-gate (DG) MOSFET for sub-threshold region, which is based on the conformal mapping technique [4],[5] .
In this paper, the approach for the analytical calculation of the electric field in [6] at the S/D metal semiconductor contacts and within the channel region by using the conformal mapping technique with 2-corner structures is analyzed in detail. Furthermore, the model is also valid for conventional MOSFETs, by a simple change of the boundary conditions. In [Figure 1], the simplified geometry of a SB-DG-MOSFET with applied boundary conditions in a complex plane z is shown. In this work, we assume a SB p-type device; nevertheless, all evolved equations can easily be converted for an n-type device. | Figure 1: Simplified geometry and boundaries of an SB-DGMOSFET in a complex plane z wherein 2D Poisson is solved. Thick lines define the S/D metal contacts and gate contacts, respectively.
Click here to view |
| 2. Calculation of the Electric Field | | |
2.1 Simplifications
In general, the electrostatic problem for an SB-DG-MOSFET can be described by Poisson's equation for the potential Φ, where the Poisson equation in the channel region with space charge ρ is
A non-doped or lightly doped device results in a negligible depletion charge (Q dep ≈ 0). Furthermore, we calculate Poisson's equation within the sub-threshold region of the device and therefore the inversion charge within the channel region can be neglected (Q inv ≈ 0). These assumptions lead to the simplification of Poisson's equation to a Laplacian equation
A method for solving 2D potential problems in an analytical way is the Schwarz-Christoffel transformation [4] . Applying this technique a region, wherein 2D Laplacian is to be solved, is conformally mapped from a complex plane z into a plane w. In this plane, all boundaries are located on the real axis and our differential equation system can be solved more easily.
In order to keep the approach for the conformal mapping technique as simple as possible, two different permittivities in the conformally mapped region are avoided. This ensures that both the dielectric flux and the electric field are continuous at the silicon-to-oxide interface. To achieve this, according to the relationship of the permeability of the SiO 2 and the Si and using the same dielectric constant as in the silicon body, the oxide thickness t ox is scaled and replaced by [5] .
Introducing this equivalent oxide thickness keeps the approach for the conformal mapping technique as simple as possible, which results in the definition of one polygon instead of three; otherwise, for each region, the definition of a polygon is necessary.
The region of interest, the shaded rectangle in [Figure 2], is cut out and a polygon with the corresponding coordinates [Figure 1] is defined, where the origin in the complex z-plane in the left lower corner and the coordinates are described by the relation z=x+jy.
2.2 Conformal Mapping and Boundary Conditions
We decompose the 4-corner problem into two 2-corner problems. The approximation made for the 4-corner problem is reasonable if the relationship l ch > t ch is valid, which usually is the case in DG MOSFETs.
The applied boundary conditions in [Figure 1] have been discussed in detail in [3] . Applying those, we receive the corresponding boundary conditions for the source- and drain-related cases, as drawn in [Figure 3] and [Figure 4]. Furthermore, V g represents the gate voltage and Vfb the flatband voltage, while Vs and Vd describe the source and drain voltage. The built-in potential at source and drain contacts is represented by φbi . The y component of the electric field within the oxide at the boundaries in [Figure 3] and [Figure 4] is assumed to be  .
By cutting out the region wherein the 2D Poisson is solved, we notice an open polygon. Several important points along the boundary [Figure 3] and [Figure 4] are marked in the complex plane z.
Applying conformal mapping technique, everything is transformed into w-plane and all points lay on the real axis, expect the arbitrary point ⑥ within the channel region, which is located upon the upper half of w-plane, see [Figure 5]. | Figure 5: The mapped region using Schwarz-Christoffel upon the upper half of w-plane is shown.
Click here to view |
where, ∆y = 2tox + tch , resulting from the device geometry. In (8) for the electric field solution, the complex conjugate of w is needed.
2.3 Solving for the Electric Field
As a basic approach to solve the electric field problem in the upper half of w-plane, an approach solving the potential problem was chosen. In [3] , a potential solution within a structure showing [Figure 6] an infinitesimal gap at position u for two electrodes along the real axis ū was used [4],[5] . | Figure 6: For two coplanar electrodes having a potential difference dφ and an infinitesimal gap at position u the potential solution is well known.
Click here to view |
Applying the Cauchy Riemann differential equations [4] , the electric field in the w-plane for the two coplanar electrodes in [Figure 6] with the potential difference dφ can be calculated in the following way.
The electric field in w-plane is expressed as
and we are able to write for
Applying the Cauchy Riemann differential equations (4) to (7) and further mathematics, which are described in detail in [6] , we receive for the electric field in w-plane
To get the electrical field strength at a corresponding point in the z-plane, (8) has to be scaled by the derivative  of the mapping function [4]
The derivative  is calculated with
Here, w is received from the conformal mapping and c is calculated with  . If we superpose several boundary conditions, each with a different position of the infinitesimal gap ū between the electrodes and several potential differences d?, then a step-like potential [3] results along the u-axis or rather a linear potential drop. For infinitesimal gaps dū between the electrodes, the potential difference is given by
Then, the superposition obtains ?(u) as boundary condition of the first order along the u-axis. With (9), the electric field strength in the complex z-plane becomes
This approach for the electric field is applied to our model. If the integration takes place along the boundaries, only contributions of the electric field with nonzero value have to be considered, because for those the integral will result in a nonzero value. This is the case for the oxide regions, where a linear voltage drop is assumed, all other parts contain constant boundary conditions with an electric field of zero. The corresponding relations between the complex w-plane and complex z-plane are used and the expression dū from  (12) is substituted with
Furthermore, we replace the expression  from the conformal mapping function [3] and  in (13) [Figure 3] and [Figure 4]. Here,  due to the linear voltage drop approximation within the oxide. ∆y results from the geometry of the device as described in section 2.2. The solution of the integral in (12) with (13) is
where, w* describes the conjugate complex point of point w where the electric field is calculated. For the source-related case results [Figure 3] the parameter w, the position of the point of interest, where the field is calculated
Applying this compact solution (14) with coordinates and boundary conditions due to [Figure 3], e.g., for the source-related case, we receive the following coordinates and boundary conditions between ②→③
The coordinates and boundary conditions between ④→⑤ are
For the source-related case, the electric field within the channel region is obtained, when both solutions are superposed.
The calculation for the drain-related case is done similarly; however, w is different due to the boundaries for  (see [Figure 4])
The solution for the overall electric field is obtained by superposing solutions from the source- and drain-related cases.
With this result, the electric field  for each position (x, y) within the channel region of an SB-DG-MOSFET can be estimated. Again, it should be noted that within this 2-corner approach, SCE are considered, because the results for the source- and drain-related case are finally superposed.
| 3. Results | | |
As we can observe in [Figure 7], with applied Vds = 1V for a SB height ɸBn = 0.28eV, our model (red lines) returns good results compared to the simulated data (black symbols) for several Vg, while we display a cut along the source electrode, outlined in [Figure 7]. Furthermore, it is observed that while we are reaching the accumulation and inversion regions, the emerging additional charge carriers begin to influence the electric field, leading to inaccuracy. | Figure 7: Electric field within an SB-DG-MOSFET at the source boundary for ɸ Bn =0.28eV. Bias conditions: V ds=1V, V g=− 0.3V to 0.2V with 0.1V steps. Device geometry: l ch=22 nm, t ch=10 nm. Lines → model, symbols → TCAD Sentaurus simulation.
Click here to view |
If we move from the source electrode to the drain electrode [Figure 8] and display the cut along the drain electrode for the identical bias conditions, we notice still a good agreement between the model for the electric field and the electric field simulated via TCAD Sentaurus. | Figure 8: Electric field within an SB-DG-MOSFET at the drain boundary for ɸ Bn =0.28eV. Bias conditions: V ds=1V, V g=− 0.3V to 0.2V with 0.1V steps. Device geometry: l ch=22 nm, t ch=10 nm. Lines → model, symbols → TCAD Sentaurus simulation.
Click here to view |
Furthermore, we appreciate an inaccuracy the closer we move to the silicon-to-oxide interface. This inaccuracy occurs from the linear approximation which we made within the oxide, as explained in [3] .
Let us take a closer look on the behavior of the electric field of the model for slices at the y axis along the x axis. First, the electric field for a cut at the middle of the channel for several Vg and Vds = 1V is shown [Figure 9]. A very good match between the model and the simulated curves from TCAD Sentaurus can be recognized. Furthermore, the inaccuracy due to the emerging charge carriers from accumulation and inversion can be noticed. Also, it can be observed that the higher Vg becomes, the closer the potential minimum  moves to the source contact. Moreover, our model predicts the intersection point in the middle of the device (l ch = 11 nm) very well. | Figure 9: Electric field within an SB-DG-MOSFET at the middle of the channel for ɸ Bn = 0.28eV. Bias conditions: V ds = 1V, V g = − 0.3V to 0.2V with 0.1V steps. Device geometry: l ch = 22 nm, t ch = 10 nm. Lines → model, symbols → TCAD Sentaurus simulation.
Click here to view |
If we move from the middle of the channel to the silicon-to-oxide interface as displayed in [Figure 10], a good agreement expect the region between 5 nm and 15 nm is observed. The deeper we move from the metal semiconductor source and drain contact into the channel, the higher the inaccuracy becomes. | Figure 10: Electric field within an SB-DG-MOSFET at the silicon-to-oxide interface for ɸ Bn = 0.28eV . Bias conditions: V ds = 1V, Vg = − 0.3V to 0.2V with 0.1V steps. Device geometry: l ch = 22 nm, t ch = 10 nm. Lines → model, symbols → TCAD Sentaurus simulation.
Click here to view |
The absolute value of the electric field within the channel region obtained by (21) is presented in [Figure 11]. As we can observe from both plots, the behavior is as expected. The Figures 12 and 13 show the real and imaginary part of the before presented electric field [Figure 11]. In [Figure 12], the real component is shown and the behavior is as expected. Near the source contact, we observe a positive electric field due to the negative gradient of the potential in accumulation. The deeper we move into the channel toward the drain contact, the electric field decreases as expected. Close to the drain contact, the gradient of the potential is positive; therefore, the electric field itself becomes negative. [Figure 13] shows the corresponding imaginary part, estimated with our analytical solution. As expected, we observe a positive and negative symmetric gradient for the imaginary components. Furthermore, a complete solution in the entire channel region is presented.
Now, with the solutions of the electrostatic potential and the electric field, the tunneling current and thermionic current can be calculated, as presented in [6] . [Figure 14] presents the estimated tunneling and thermionic currents of our model compared to TCAD Sentaurus [7] overall current simulations. Currently, we calculate the tunneling current without the effect of SB lowering, using the Wentzel-Kramers-Brillouin (WKB) approximation [8] . | Figure 14: Tunneling and thermionic current for ɸ Bn =0.28eV. Bias conditions: V ds=0.4V to 1V with 0.2V steps, V g=− 0.5V to 1V with 0.1V steps. Device geometry: l ch = 45 nm, t ch = 20 nm, w ch = 1 µm . Lines → model, symbols → TCAD Sentaurus simulation.
Click here to view |
| 4. Conclusion | | |
An analytical approach to calculate the electric field in SB-DG-MOSFETs was presented. The approach is valid for sub-threshold region and does not introduce any fitting parameters; all parameters depen d on geometry and boundary conditions. The 2D Poisson's equation has been solved using the conformal mapping technique. With a detailed analysis of the real and the imaginary parts of the electric field solution, the approach has been validated. This approach shows a good agreement with the simulation results from TCAD Sentaurus for 22 nm channel length. This model can be used to calculate S/D-related tunneling currents in an analytical closed form which is suitable for compact models. A result of the tunneling and thermionic currents in an SB-DG-MOSFET device was presented, calculated with the here explained approach.
| 5. Acknowledgment | | |
This project was supported by the German Federal Ministry of Education and Research under contract No. 1779X09, by the German Research Foundation (DFG) under Grant KL 1042/3-1, and by the European Commission under FP7 Projects ICT-216171 ("NANOSIL") and IAPP-218255 ("COMON"), by the Spanish Ministerio de Ciencia y Tecnología under Projects TEC2008-06758- C02-02/TEC, and also by the PGIR/15 Grant from URV and by the ICREA Academia Prize.
| References | | |
| 1. | N Collaert, A De Keersgieter, A Dixit, I Ferain, L S Lai, and D Lenoble, et al, "Multi-gate devices for the 32nm technology node and beyond." in Proc. 37th European Solid State Device Research Conference ESSDERC2007, pp. 143-6, 2007. 
|
| 2. | J M Larson, and J P Snyder, "Overview and status of metal S/D Schottky-barrier MOSFET technology." IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-58, 2006.
|
| 3. | M Schwarz, M Weidemann, A Kloes, and B Iñíguez, "2D Ana-lytical calculation of the electrostatic potential in lightly doped Schottky barrier double-gate MOSFET." Solid-State Electronics, vol. 54, No. 11, pp. 1372-80, 2010.
|
| 4. | E Weber, "Electromagnetic fields," Vol. I., Mapping of fields. New York: John Wiley; 1950.
|
| 5. | A Kloes, and A Kostka, "A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling." Solid-State Electronics, vol. 36, no. 12, pp. 1761-75, 1996.
|
| 6. | M Schwarz, T Holtij, A Kloes, and B Iñíguez, "2D Analyti-cal calculation of the electric field in lightly doped Schottky barrier double-gate MOSFETs and estimation of the tunnel-ing/thermionic current." in Press: Solid-State Electronics, 2011.
|
| 7. | Synopsys, TCAD Sentaurus. Synopsys, Inc., c-2009.06 ed., 2009.
|
| 8. | G Wentzel, "Eine Verallgemeinerung der Quantenbedingungen für Würfel Zwecke der Wellenmechanik." Z. Physik, vol. 38, pp. 518-29, 1926.
|
| Authors | | |
Mike Schwarz received his diploma degree at University of Applied Sciences Giessen- Friedberg, Giessen, Germany, in 2008. He was awarded the Friedrich-Dessauer-Prize for the best diploma thesis about multiclass support vector machines.
In 2009, he received his M.S. degree in electrical engineering from the Universitat Rovira i Virgili, Tarragona, Spain.
In 2010, he obtained the URV Graduated Student Meeting on Electronic Engineering Award for the best oral presentation for a paper about an analytical model for the electric field in Schottky Barrier Double-gate MOSFETs.
Since 2008, he is working as research assistant in the Device Modeling Research Group at the Competence Center for Nanotechnology and Photonics at the Technische Hochschule Mittelhessen, Giessen, Germany.
He is currently with Technische Hochschule Mittelhessen and pursuing his Ph. D. degree in Tarragona as well. The main focus of his doctoral research is compact modeling of Schottky Barrier multiple-gate FETs.
His current research interests are Schottky Barrier MOSFET devices and compact modeling.
Thomas Holtij received his diploma degree at University of Applied Sciences Giessen- Friedberg, Germany, in 2010. He obtained the Friedrich-Dessauer-Prize for the best diploma thesis about analytical modeling of the parasitic resistances in multiple-gate FETs.
He is currently with Technische Hochschule Mittelhessen and pursuing his M.S. degree in electrical engineering from the Universitat Rovira i Virgili, Tarragona, Spain.
His current research interests are Double- gate MOSFET devices and compact modeling.
Alexander Kloes received his diploma and Ph. D. in electrical engineering at Technical University of Darmstadt, Solid-State Electronics Laboratory, Darmstadt, Germany, in 1993 and 1996, respectively.
He has worked as Project Manager R&D at Braun GmbH, Kronberg, Germany, from 1997 to 2002, where he focused on IR sensor technology on silicon.
Since 2002, he is Professor at Technische Hochschule Mittelhessen, Giessen, Germany. He is heading the Device Modeling Research Group at the Competence Center for Nanotechnology and Photonics.
His research interests are in semiconductor device modeling, especially for nanoscale MOS devices.
Prof. Kloes is associated member in COMON (Compact Modelling Network), an Industry Academia Partnership and Pathway funded by the 7th Framework Programme of the European Commission. In this context, he is contributing to the research group at Universitat Rovira i Virgili, Tarragona, Spain. Framework Programme, IAPP Project), contributing to the research group at Universitat Rovira i Virgili, Tarragona, Spain.
Benjamín Iñíguez received the B. S., the M. S., and the Ph. D. Degrees in physics from the University of the Balearic Islands (UIB), Spain, in 1989, 1992, and 1996, respectively. His doctoral research focused on the development of CAD models for short-channel bulk-Si and SOI MOSFETs.
From February 1997 to September 1998, he was working as a Postdoctoral Research Scientist at the ECSE Department, Rensselaer Polytechnic Institute (RPI), Troy, NY, in 1997-1998, where he studied advanced devices, such as short-channel a-Si and poly-Si TFTs, GaN HFETs and heterodimensional MESFETs.
From September 1998 to February 2001, he was a Research Scientist (Postdoctoral Marie-Curie Grant Holder) in the Microelectronics Laboratory, Universite Catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, working on the characterization and modeling of thin-film and ultrathin-film SOI MOSFETs from DC to RF conditions.
In February 2001, he joined the Department of Electronic Engineering (DEEEA), Universitat Rovira i Virgili (URV), Tarragona, Spain, as Titular Professor. In 2004, he was awarded the Distinction of the Catalan Government for the Promotion of University Research. In 2007, he was awarded the IET Premium Award for a paper about charge transport in organic TFTs.
His current research interests are characterization and modeling of advanced electron devices, in particular nanoscale multiple-gate MOSFETs and organic and polymer TFTs. He is IEEE Senior Member from 2003, and IEEE EDS Distinguished Lecturer since 2004. In 2009, he obtained the ICREA Academia Prize. In 2010, he became Full Professor at the Universitat Rovira i Virgili (URV).
He has authored or co-authored more than 80 papers in international journals and a similar number in international conferences. He has participated in several European projects, and he is the leader of the "COMON" (Compact Modelling Network), an Industry Academia Partnership and Pathway funded by the 7th Framework Programme of the European Commission.
[Figure 1], [Figure 2], [Figure 3], [Figure 4], [Figure 5], [Figure 6], [Figure 7], [Figure 8], [Figure 9], [Figure 10], [Figure 11], [Figure 12], [Figure 13], [Figure 14]
|
