|Year : 2012 | Volume
| Issue : 3 | Page : 214-221
RF Compact Modeling of High-voltage MOSFETs
Antonios Bazigos1, François Krummenacher1, Jean-Michel Sallese1, Matthias Bucher2, Ehrenfried Seebacher3, Werner Posch3, Kund Molnár3, Mingchun Tang3
1 Ecole Polytechnique Fédérale de Lausanne, CH-1015, Ecublens, Swaziland
2 Technical University of Crete, 73132 Chania, Greece
3 Austriamicrosystems AG, 8141 Unterpremstaetten, Austria
|Date of Web Publication||16-Jun-2012|
Ecole Polytechnique Fédérale de Lausanne, CH-1015, Ecublens
| Abstract|| |
The High-Voltage MOSFET is used in a wide variety of applications covering from power systems up to RF-IC. Compact models that describe the high-frequency behavior of the device are required to predict high-frequency operation and switching capabilities of these elements in HV state-of-the-art systems. In this paper, an RF model is presented and verified against extensive Y-parameter measurements, which were carried out on a long channel Lateral double-Diffusion MOS device. Assessment of the model with measurements confirms the validity of this approach.
Keywords: Drift region, High-frequency regime, High-Voltage MOSFET, HV-MOS, LDMOS, Physics-based analytical compact model, RF
|How to cite this article:|
Bazigos A, Krummenacher F, Sallese JM, Bucher M, Seebacher E, Posch W, Molnár K, Tang M. RF Compact Modeling of High-voltage MOSFETs. IETE J Res 2012;58:214-21
| 1. Introduction|| |
The importance of the High-Voltage (HV-MOS) as a device in state-of-the-art applications has been reported extensively in scientific literature ,,,, . One of the reasons is that modern HV-MOS devices, like Lateral double-Diffusion MOS (LDMOS), may be integrated together with low-voltage modules in CMOS processes , . The systems, where such devices are used, range from power components for automotive and consumer products  up to radio frequency applications ,, . Therefore, compact modeling of HV-MOS is an enabling factor that will help in predicting how these devices can be optimally integrated in complex architectures ,,,,,,,,,,,,,,,,,. More particularly, the RF characterization and modeling of HV-MOS should receive extra attention since the high-frequency behavior is, still, a quite demanding and challenging issue. The results presented here are a continuation of a previous work that has already been published  .
| 2. Model Description|| |
The structure of an HV-MOS, if simplified, may be regarded as the in series combination of two simpler elements. On one side lays the low-voltage part which closely resembles to a classical MOSFET, except for the relatively high longitudinal doping gradient across the channel , . On the other side, beyond the inner drain of the low-voltage part there is the high-voltage section which protects the low-voltage MOSFET from excessively high potentials. This part, also called drift region, has the same type doping as the outer drain and source of the HV-MOS. Its quite long extension, i.e., a few microns, ensures safe operation needed for the device to function at dozens of volts  .
The compact model used in this work takes advantage of the above simplification, describing the whole structure as a macromodel of two basic elements. The connection of these two elements takes place at a node called the K-point, which is, in physical terms, the metallurgical junction point where the doping profile changes its type, between the channel of the low-voltage part and the drift region , . In order to model the device at RF, additional extrinsic components must be added. Among them, there are a gate resistance and two asymmetrical junction diodes between the source and the drain terminals and the substrate. In addition, it has been observed that overlap capacitances between the gate and other nodes are not negligible. These overlap capacitances become even more important for specific small geometries.
The elements of the intrinsic part of the model can be considered as a small signal equivalent network built upon transcapacitances and current sources. For the core of the model, and omitting higher order effects like impact ionization current, the low-voltage part of the device can be represented by three transcapacitances between the gate and other nodes, and a current source between the K-point and the source node. In addition, a similar representation can de adopted for the drift region. Here, again a current source is needed between the outer drain and the K-point, and also two transcapacitances, one between the gate and the K-point that describes the charge behavior of the carriers just below the oxide, and one more between the gate node and the outer drain, which accounts for the charges laying in the rest of the drift region. This is sketched in the small signal equivalent circuit schematic of [Figure 1].
|Figure 1: Small Signal equivalent circuit of the macromodel for the HV-MOS. The intrinsic and extrinsic parts are shown, while the intrinsic part is further divided into the low-voltage part and the drift region. For the intrinsic part, transcapacitances and current sources are used, while the extrinsic part consists of junction-diodes, resistors, and capacitors.|
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2.1 Dynamic Charge Behavior of the Drift Region
The dynamic behavior of the low-voltage part of the device including a MOSFET with lateral non-uniform doping is analyzed in ,,, , while a detailed analysis of the charge has been discussed in  . In this article, the discussion on the dynamic behavior of the HV-MOS devices will be pursued by giving a transcapacitance representation of the charges in the drift region.
Considering the charge-sheet approximation  , the charge of the drift region may be considered as the sum of two components. The first component (q k ) is the charge accumulated just below the thin oxide and has been analyzed in  . If W DK and L OV.DK are the width and the effective gate length overlap the drift region, respectively, and T OX is the effective thickness of the thin oxide above the drift region, then the total charge at the K-point is calculated from:
Where, εOX is the permittivity of the oxide, and q k and Q K.DK are respectively the normalized and absolute charge densities  .
On the other hand, the sum of the charge in the drift region will be equal (in absolute value and opposite in sign) with the charge that will accumulate at the gate node (Q G.DK ). If Q D.DK denotes the charge at the inner part of the drift region, we get:
Note that Q G.DK stands only for the part of the gate charge that is connected with the drift region, and does not represent the whole charge of the gate node. This charge may be calculated after the following equation.
In the above equation, V FB.DK denotes the Flat-Band voltage of the drift region and the ΨK is the surface potential at the K-point. The latter is calculated from the potential of the internal node of the K-point (V K ), which is evaluated considering the continuity of the current at the K-point  . Therefore, the above set of equations form the core of the model for the dynamic behavior of the drift region.
| 3. Comparison with Measurements|| |
The model has been verified against numerical simulations of Technology Computer-Aided Design (TCAD) tools and real measurements  . Few selected results will be presented in this section in order to demonstrate its capabilities. For this purpose, an LDMOS device has been chosen with a minimum gate length of L = 500 nm. The gate width is W = 40 μm, while the thickness of the oxide is T OX = 15 nm in order to withstand a gate potential up to 5 V.
3.1 Static Current Aspects
In [Figure 2], a comparison between the model and measurement for various static current conditions is presented. The model shows good capabilities under all bias conditions. The device's behavior is more complicated than the classical MOSFET case since there is a continuous balance between the two parts of the device that sets the quasi-fermi potential of the K-point. In principle, it could be said that for low gate potential, when the channel of the low-voltage MOSFET of the device is in weak inversion, the overall device acts similarly to a classic MOSFET having a resistive load at its drain. As the inversion level increases and the low-voltage part gets deeper in strong inversion, more and more carriers can be provided to the drift region. Under these bias conditions, it is the drift region that will govern the overall behavior of the device, especially for high V DS values, and the device differentiates importantly from the classic MOSFET.
|Figure 2: Static current measurements (markers) and model behavior (lines) of an LDMOS (L=500 nm, W=40 mm, TOX=15 nm). The two plots on the left are an I D vs. V G analysis with a low value for VDS=100 m and for various VSB values between 0V and 4.5V. The two plots in the middle repeat the same analysis with high value for V DS=35 V. The two plots on the right illustrate and I D vs. V D where VSB=0V and V GS ranges between 1V and 5.5V. The upper graphs show the current while the lower either the transconductance, gm for the analyses I D vs. V G, or the output conductance, gds, for the I D vs. V D analysis|
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3.2 Dynamic Behavior Analysis
In order to validate the model according to its dynamic behavior, the LDMOS device was also measured at high frequencies. Considering the device as a two-port network, where the input (port 1) is between gate and source, and the output (port 2) is between drain and source (which is connected to the ground), S-parameter measurements were performed up to 6 GHz. The measurements were done under various bias conditions. When V DS was zero, the gate potential varied between -4V and 4V, while with positive V DS, the gate potential swept between 0.8V and 4.8V. The S-parameters were transformed to Y-parameters, which are better suited for the voltage-to-current terminology already used in static analysis. [Figure 3] shows some selective results of the above measurements for a specific frequency, f = 1.2 GHz, displayed along with the simulation obtained from the model. The model covers adequately the high-frequency behavior of the device under an extended range of bias conditions providing good results in terms of Y-parameters for all modes of operation.
|Figure 3: Y-parameters, in real and imaginary part, of an LDMOS device with geometric parameters of L=500 nm, W=40 mm, and T OX=15 nm. The markers (V DS=0V: ○ and V DS=30V: ◊) are for measurements while the lines are the model's behavior. Port 1 is gate-to-source and port 2 is drain-to-source, and V SB=0V. The results are shown for frequency f=1.2GHz.|
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| 4. Extrinsic Network and RF Parameter Extraction|| |
In this section, a short analysis on the parameter extraction procedure will be discussed. It shall be focused on the extraction of the parameters related to the extrinsic part of the device which may benefit from the high-frequency analysis of the device ,,, . Although the core of the following techniques is based on the classic MOSFET, it shall be shown that there is enough space for its application to HV-MOS devices.
4.1 Gate Resistance
By analyzing the small signal equivalent circuit, and its functionality under small signal conditions, the gate resistance can be estimated by the following equation , .
In [Figure 4], the estimation of the gate resistance is plotted against the gate potential for the LDMOS device under test. The extraction of the value of the gate resistance is best performed under negative gate bias conditions and with V DS = 0V, since this bias minimizes the influence of the rest of the device. For the simulations shown here, a value of 90Ω has been used for RG which is very close to the estimation of (4) for low enough values of the gate potential. These results verify that this equation is valid for the HV-MOS devices as well.
|Figure 4: The Gate Resistance (R G) as estimated by (4) under various bias conditions with V SB=0V and f=1.2 GHz, for an LDMOS device with L=500 nm, W=40 mm and T OX=15 nm. Markers stand for measurements (V DS=0V: ○ and V DS=30V: ◊), while lines are model simulations. The accurate value of the resistance is best extracted under negative gate bias and zero drain-to-source difference potential, as these conditions minimize the influence of the rest of the device. Here, the RG used for the model is 90Ω. The dotted line is for the simulation of the model minimizing the gate resistance.|
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Viewing the transistor as a two-port network, the imaginary parts of the Y-parameters hold information on the capacitances and the transcapacitances of the devices. This way, the following equation, which contains Im(Y 11 ), can be used as an estimation of the capacitance seen from the gate node, meaning the total gate capacitance.
In [Figure 5], an estimation of the total gate capacitance is shown against the gate potential. The profile resembles to the classical MOSFET one, where the regions of operation of the device according to the gate potential are well separated, especially for the V DS = 0V case. For the lowest values of the gate potential, the gate capacitance is maximized as the device works in accumulation. As the gate potential increases, the area below the thin oxide gets depleted and the device enters in depletion. Further increment of the gate potential leads to an inversion layer where the total gate capacitance reaches again its maximum value  . Under a positive V DS , the device shows some clear deviation with respect to corresponding basic MOSFET device. Due to Miller effect, the total gate capacitance exceeds the maximum expected and exhibits a different shape .
|Figure 5: Total Gate Resistance (C GG) as estimated by (5), under various bias conditions with V SB=0V and f=1.2 GHz, for an LDMOS device with L=500 nm, W=40 mm, and T OX=15 nm. Markers stand for measurements (V DS=0V: ○ and V DS=30V: ◊), while lines are model simulations.|
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The rest of the Y-parameters can be used in order to extract information on the extrinsic capacitances, see [Figure 6]. These can be obtained from the following relationships.
|Figure 6: Various capacitances and transcapacitances as estimated by (6), (7), and (8), under various bias conditions with V SB=0V and f=1.2 GHz, for an LDMOS device with L=500 nm, W=40 μm, and T OX=15 nm. The non-filled markers stand for measurements with V DS=0V and the filled markers for V DS=30V, while the lines show the model simulation. The dotted lines represent the contribution of the junction diode capacitance to C DD, while the dashed lines stand for the contribution of the extrinsic, gate-to-drain, overlap capacitance to C DD.|
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Similarly, to the total gate capacitance, the Im(Y 22) represents the capacitance of the device seen from the drain node. A major component of C DD is the junction diode capacitance. On the other hand, one can see that at low and negative gate potentials, the estimations of C GD and C DG coincide. By inspection of the equivalent small-signal circuit, C DD may be regarded as the sum of the extrinsic overlap capacitance between the gate and the drain (C GD.OV) with the gate-to-drain capacitive load of the drift region. If this sum is substracted from C DD, under the same bias conditions, the rest holds for the drain-to-substrate parasitic junction diode (C J.DB) capacitance. Again, these parasitic elements are magnified for negative gate biases, where the channel does not influence the overall behavior of the device. Note that, under positive V DS, the reciprocity between these two transcapacitances breaks down due to the saturation of the device from the drain side.
[Table 1] displays the related models parameters used for the above analyses.
| 5. Conclusion|| |
Compact modeling of High-Voltage MOS devices is critical and merits a careful analysis at RF. In this work, we present an RF HV-MOS model along with its core equations that provides good results up to the GHz range of frequency. Further analysis of the dynamic behavior of the HV-MOS verifies the adequacy of the foundations of our RF model in terms of equivalent circuit built upon passive elements.
| 6. Acknowledgment|| |
The research leading to these results has received funding from the European Community's Seventh Framework Programme (FP7/2007-2013) under grant agreement N°218255.
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| Authors|| |
Antonios Bazigos was born in Athens, Greece, in 1980. He received the Diploma in electrical and computer engineering and the Ph.D. degree from the National Technical University of Athens (NTUA), Athens, in 2003 and 2008, respectively. His Ph.D. thesis is on the field of compact modeling of the MOS transistor. Currently, he is a Postdoctoral Researcher with the Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland, on high-voltage MOS field-effect transistor modeling, within the framework of the Compact Modeling Network project. He has worked on the development and the code implementation of the EKV3 MOS transistor compact model, and he is still working on the further improvement of the model.
François Krummenacher was born in Lausanne, Switzerland, in 1955. He received the M.S. and Ph.D. degrees in electrical engineering from Swiss Federal Institute of Technology (EPFL), Lausanne, in 1979 and 1985, respectively. He has been with the Electronics Laboratory, EPFL, since 1979, working in the field of low-power analog and mixed-signal complementary metal-oxide-semiconductor (MOS) integrated circuit (IC) design, as well as in deep submicron and high-voltage MOS field-effect transistor device compact modeling. Since 1989, he has been also working as an Independent Consultant, providing scientific and technical expertise in IC design to numerous local and international industries and research laboratories. He is the author or coauthor of more than 100 scientific publications in these fields.
Jean-Michel Sallese received the M.Sc. degree from the Institut National des Sciences Appliques, Toulouse, France, and the Ph.D. degree in physics from the Centre National de la Recherche Scientifique, University of Nice-Sophia Antipolis, Nice, France, where he worked on deep-level characterization in semiconductors.
He has been with the Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland, since 1991, where he was involved in III-V laser diode activities and modeling interdiffusion phenomena in quantum wells and quantum wire structures. He currently gave lectures in the modeling of semiconductor devices in the context of circuit design, and his research activities concern compact modeling of bulk and multigate metal oxide-semiconductor field-effect transistors, as well as modeling of emerging microelectromechanical systems.
Matthias Bucher received the Diploma in electrical engineering and the Ph.D. degree from the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 1993 and 1999, respectively. The subject of his Ph.D. thesis was the analytical metal-oxide-semiconductor (MOS) transistor modeling for analog circuit simulation.
In 1997, he was an Invited Researcher with Large Scale Integration Logic, Milpitas, CA. From 2000 to 2003, he was a Visiting Researcher with the National Technical University of Athens, Athens, Greece, and was a Consultant for the microelectronic industry. In 2004, he was an Assistant Professor with the Department of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece, where he currently is the Director of the Electronics Laboratory. His research interests are in the design of low-voltage low-power analog/radio-frequency integrated circuits and in the broadband characterization and advanced compact modeling of nanoscale complementary-MOS devices. He has also coordinated the EKV3 MOS transistor compact model code development. He has authored or coauthored numerous scientific papers.
Ehrenfried Seebacher was born on September 3, 1966. He received the M.Sc. degree in physics from the Technical University of Graz, Graz, Austria, in 1993.
From 1994 to 1998, he was with the Department of Research and Development, austriamicrosystems, Unterpremstδtten, Austria, working on compact modeling of complementary metal-oxide-semiconductor (CMOS), bipolar CMOS, and high-voltage CMOS processes. Since 1999, he has been the Section Manager of the said group at austriamicrosystems. The group is responsible for compact modeling, process characterization, verification run sets, and Simulation Program with Integrated Circuit Emphasis (SPICE) simulator support. He has supervised a number of students in research dealing with compact modeling and SPICE simulation. His research interests include modeling of MOS, bipolar transistors, and passive elements.
Werner Posch was born in Tamsweg, Austria, in 1974. He received the M.S. degree in applied physics from Graz University of Technology, Graz, Austria, in 2002. He is currently working toward the Ph.D. degree at Graz University of Technology, with an emphasis on mismatch modeling for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) processes.
He is currently with the Process and Device Characterization Group, austriamicrosystems, Unterpremstδtten, Austria, where his primary activity is HV laterally diffused (LD) MOS transistor Simulation Program with Integrated Circuit Emphasis modeling. His research interests include matching characterization of HV-LD MOS transistors and capacitor arrays.
Kund Molnαr was born in Nyiregyhaza, Hungary, in 1970. He studied solid-state electronics and received the Dipl.-Ing. degree in electrical engineering from the Technical University of Ilmenau, Ilmenau, Germany, in 1994, and the Ph.D. degree in applied physics from Budapest University of Technology and Economics, Budapest, Hungary, in 2002.
Between 1995 and 1998, he was a Research Assistant with the Research Institute for Technical Physics and Materials Science (MFA), Budapest, investigating carrier transport in porous silicon light-emitting diodes. In 1999, he became a Member of the Budapest Design Center, austriamicrosystems AG, Unterpremstδtten, Austria. In 2000, he joined the headquarters in Unterpremstδtten, where he is currently working on analog/radio frequency Simulation Program with Integrated Circuit Emphasis modeling of semiconductor devices.
Mingchun Tang was born in Fushun, China, in 1979. He received the B.S. degree in applied physics from Jilin University, Changchun, China, in 2002, and the M.S. and Ph.D. degree in the field of compact modeling of advanced metal-oxide-semiconductor transistors, such as fin-shaped field-effect transistors, from the University of Strasbourg, Illkirch, France, in 2006 and 2009, respectively.
Since 2010, he has been with austriamicrosystems, Unterpremstaetten, Austria, as Simulation Program with Integrated Circuit Emphasis Modeling Engineer.
[Figure 1], [Figure 2], [Figure 3], [Figure 4], [Figure 5], [Figure 6]