|Year : 2012 | Volume
| Issue : 3 | Page : 237-242
Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors
Lorenzo Labate, Simona Angela Cozzi, Roberto Stella
Technology R&D Smart Power & High Voltage Group, STMicroelectronics, 20010 Cornaredo, Via Tolomeo, MI, Italy
|Date of Web Publication||16-Jun-2012|
Technology R&D Smart Power & High Voltage Group, STMicroelectronics, 20010 Cornaredo, Via Tolomeo, MI
| Abstract|| |
Many applications affecting our daily life require devices that can reach very high voltages. These applications are generally controlled by a logic shifted up to, for example, 600 V with respect to the ground. The device adopted in order to let high-voltage world talk with low-voltage logic is a level shifter, here nicknamed "Mickey Mouse" due to its particular shape. Since it can be composed by several elements, such as linear, curved, and ball-shaped transistors (ears of "Mickey Mouse"), the model has to take into account the scalability of the device in terms of linear width, number of curves, and number of ears. Extraction strategy and methodology used to achieve an accurate model will be presented in this work.
Keywords: BSIM3, HV MOS, Level shifter, Modeling
|How to cite this article:|
Labate L, Cozzi SA, Stella R. Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors. IETE J Res 2012;58:237-42
| 1. Introduction|| |
Integrated components that can sustain the power line or greater voltages offer a big advantage in terms of circuit integration. In fact, the traditional coil transformers can be avoided and, for example, the well-known low consumption bulbs are realized. Moreover, since these components have been developed in a 0.35-μm smart power technology, BCD6SOFFLINE  , which can integrate in the same wafer CMOS 3.3V/5V/20V, BJTs, passives, MV MOS, and 600V/800V MOS, the opportunity to translate in an IC a 3.3 V logic signals into 600 V ones is given. This allows driving very carefully, with a precise logic signal, a high-voltage or high-power device. For this case, motor drivers used for brushless DC motors (BLDC) are an excellent example ,,, . They are driven at high voltage and high power by dedicated components like IGBT, but at the same time, they are controlled very carefully in terms of current phases and rotor position. These BLDC motors can be easily found in consumer products, food processors, air conditioners, and are also adopted in automotive field, for fuel/water pump and electric car  .
| 2. Realization of an Integrated Level Shifter|| |
Referring to [Figure 1], the level shifter is composed by different active elements, Lateral Double Diffused MOS (LDMOS), and passive ones used for isolation of the internal pocket. In the figure, three active elements are highlighted. The first is the floating pocket (detail FP, [Figure 1]), where the low-voltage 3.3 V logic is placed. The floating pocket can be shifted with respect to the ground of hundreds of volts. The ears of "Mickey-Mouse" (detail E, [Figure 1]) represent the second element. They are realized with a LDMOS [Figure 2] and are used to bring signals inside and outside the floating pocket. Finally, the perimeter element, P, is put in evidence. It is realized with a LDMOS too and is needed to bring out the HV signal.
The geometric dimensions of this particular level shifter are not defined "a priori."
The perimeter and the number of ears are defined by FP area, which depends on the complexity of the circuit to be drawn inside it, and by performances required for LDMOS transistors.
| 3. Modeling Strategy|| |
The goal of our work is the extraction of a fully scalable model, able to describe both the perimeter and the ears transistors, giving the designers the maximum flexibility during the definition of the project. To reach the scope, two model cards have been obtained, one for perimeter, scalable with number of curves and total linear channel width, and the other for ear, scalable with number of ears.
The target device, shown in [Figure 3]a, is composed both by a perimeter and by two ears transistors, which can be measured independently.
In addition to target device, a round MOS is also present. It is a fixed width transistor, with the same curvature radius and layout parameters of target one. Round MOS device, shown in [Figure 3]b, has been used as starting point of modeling work, to extract intrinsic MOS model parameters (BSIM3 model  ), drain drift resistance parameters and parasitic elements. A dedicated model card has been released to describe the stand-alone round MOS device.
For target device, instead, a model card composed by two branches has been created. A MOS device and a non-linear resistor compose each branch. One branch has been used to describe linear channel width behavior and the other to describe the curvilinear one [Figure 4]. The electrical behavior of the curvilinear MOS has been characterized on ears device, which is indeed mainly curvilinear, since it can be described as six curves, for a total curvilinear channel width greater than 1.5 mm, plus a negligible linear width. The electrical behavior of linear MOS, instead, has been characterized on perimeter device, which can be described as two curves and a very large linear channel width.
In order to take into account the parasitic elements present in the "Mickey Mouse." several components have been added. An NPN bipolar transistor has been introduced to simulate the Source/Body/Drain junctions and a PNP transistor has been used to simulate Body/Drain/Substrate junctions. Since these bipolar transistors have a common junction, Body/Drain, their behavior is mutually influenced. In particular, the collector resistance of parasitic NPN, called RCB, acts also as Base resistor for parasitic PNP. Its value is drastically reduced if Body/Drain or Substrate/Drain junction is forward biased because the drain effective doping is modulated by high injection effects. Therefore, RCB has been modeled by a non-linear resistor controlled by base current of parasitic PNP.
It should be noted that Drain/Gate and Drain/Body capacitances are affected by RESURF effect , , as clearly shown in [Figure 5]. The modeling approach to RESURF junction Capacitance is to describe the plot as sum of two junctions like capacitance with a transition region, as reported in  . A similar approach has been used also to describe Gate/Drain capacitance, which is expressed as the sum of two MOS capacitances combined by a smoothing function:
Where, V BIAS is the voltage applied to the capacitor, C1,2 are zero-bias capacitances, K 1,2, VFB 1,2, MJK 1,2, ε1,2 are MOS capacitor parameters, and V STEP, ε, and N are transition factors.
The resulting sub-circuit used for modeling "Mickey Mouse" devices is reported in [Figure 4].
| 4. Results|| |
To show the model accuracy, we reported the comparisons between measurement and simulation. Starting from Round MOS, the model accuracy for drain current and small signal trans-conductance (gm) are shown in [Figure 6]. In [Figure 7], model scalability in linear region is reported since trans-characteristics of all devices are shown. The saturation region behavior is reported in [Figure 8] and [Figure 9]. In [Figure 8], the output characteristic of the Round MOS completely turned on are reported. In [Figure 9], it is shown the electrical device behavior up to 800 V of Drain-Source voltage, for low Gate-Source voltage values. Linear region model accuracy in the whole temperature range, from -40°C to 175°C, is shown in [Figure 10]. About the parasitic bipolar transistors, the current gain of both NPN transistor, which is associated with Source/Body/Drain junctions, and of PNP transistor, which is associated with Body/Drain/Substrate junctions, are reported in [Figure 11]. Finally, parasitic capacitances plots relative to junctions and gate oxide are reported in [Figure 5].
|Figure 7: Trans-characteristic in linear region for the three tested structures.|
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|Figure 10: Round MOS linear trans-characteristic behavior over temperature range.|
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| 5. Conclusions|| |
"Mickey Mouse" level shifter has been described by the union of two models, which are able to model both perimeter and ear behaviors. Extracted models are fully scalable and able to satisfy all needs of electronic designers. All active and passive elements related to the structure of HV MOS transistors have been included in the models. RESURF effects have been accurately modeled to take into account the modulation of drift region resistance and involved capacitances.
| 6. Acknowledgment|| |
We would like to thank R. Depetro for the helpful discussion, explanation, and patience; A. Morello for the discussion over the design; and E. Novarini for his support and trust on us.
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| Authors|| |
Lorenzo Labate was born in Abbiategrasso (Milan), Italy, in 1969. He received the diploma degree in industrial electronics from Technical Industrial Institute "E. Alessandrini" of Abbiategrasso. Since 1990 he has been with STMicroelectronics, Milan, Italy, and in the Technology R&D group fully devoted to the electrical characterization of BCD technologies. In particular for characterization of NVM embedded in a mixed technology, developing of MEMS accelerometer, characterization and modeling of: RF DMOS transistors, SOI devices including self-heating effects, HV transistors, integrated JFET.
Simona Angela Cozzi received the degree in physics in 1999 from the University of Milan, Italy. Since 2000 she joined STMicroelectronics, Milan, Italy, in Quality & Reliability Flash Memory group and, from 2004 in the Technology R&D group, devoted to components electrical characterization and modeling of BCD technologies. She looks after about modeling of HV transistors and new concept devices in SOI and bulk technologies.
Roberto Stella graduated in Physics at the University of Milan in 1989 with a thesis work about the modeling of the VDMOS transistor. Since 1989, he has been working in STMicroelectronics involved in the electrical characterization and modeling of devices in smart power technologies. Presently he manages the group dedicated to the extraction of compact models for all BCD technologies. He published many papers about modeling and characterization of Smart Power technology devices.
[Figure 1], [Figure 2], [Figure 3], [Figure 4], [Figure 5], [Figure 6], [Figure 7], [Figure 8], [Figure 9], [Figure 10], [Figure 11]