http://www.jr.ietejournals.org/currentissue.asp IETE J Res 2012 - 58(3) IETE Journal of Research Medknow Publications0377-2063 AB Bhattacharyya Wladek Grabinski Editorial IETE Journal of Research 2012 58(3):179-180doi:10.4103/0377-2063.97322 IETE Journal of Research 10.4103/0377-2063.97322 http://www.jr.ietejournals.org/text.asp?2012/58/3/179/97322 http://www.jr.ietejournals.org/text.asp?2012/58/3/179/97322583 179 180 http://www.jr.ietejournals.org/text.asp?2012/58/3/179/97322 AB Bhattacharyya, Wladek Grabinski

IETE Journal of Research 2012 58(3):179-180

]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/179/97322 Mike E Brinson Stefan Jahn H Nabijou Article IETE Journal of Research 2012 58(3):181-190doi:10.4103/0377-2063.97323 IETE Journal of Research 10.4103/0377-2063.97323 http://www.jr.ietejournals.org/text.asp?2012/58/3/181/97323 http://www.jr.ietejournals.org/text.asp?2012/58/3/181/97323583 181 190 http://www.jr.ietejournals.org/text.asp?2012/58/3/181/97323 Mike E Brinson, Stefan Jahn, H Nabijou

IETE Journal of Research 2012 58(3):181-190

Conventional modeling and simulation of two-phase switched current MOS-integrated circuits is normally undertaken at semiconductor device level. This allows primary and secondary circuit effects to be studied and characterized. However, with the growing complexity of these circuits, transient domain simulation times can become prohibitively long, restricting the size of circuit that can be easily investigated. Measurable reductions in transient simulation run times can be achieved by modeling part, or all, of a switched current design as a macromodel. This paper introduces a hybrid approach to MOS switched current circuit modeling that combines the primary features of compact device modeling with functional circuit macromodeling. To illustrate the proposed hybrid modeling procedure the properties, and simulation model, of a MOS switched current analog memory cell are described. The material presented also demonstrates how recent trends in "Quite universal circuit simulator" (QUCS) technology promote embedded Verilog-A models and equation-defined subcircuits as integral elements in mixed-mode circuit and system design.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/181/97323 Filippo Alagi Roberto Stella Emanuele Viganó Article IETE Journal of Research 2012 58(3):191-196doi:10.4103/0377-2063.97324 IETE Journal of Research 10.4103/0377-2063.97324 http://www.jr.ietejournals.org/text.asp?2012/58/3/191/97324 http://www.jr.ietejournals.org/text.asp?2012/58/3/191/97324583 191 196 http://www.jr.ietejournals.org/text.asp?2012/58/3/191/97324 Filippo Alagi, Roberto Stella, Emanuele Viganó

IETE Journal of Research 2012 58(3):191-196

Usually, aging models implemented in design kits are able to accurately describe parameter degradation only if kinetics during constant voltage stress is relatively simple; a methodology is proposed to extend aging simulation to a more complex behavior, and indeed implementable into a commercial software environment (in the case Eldo UDRM by Mentor Graphics). The methodology is applied to describe Ron drift of a 40 V Nch MOS transistor.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/191/97324 Mike Schwarz Thomas Holtij Alexander Kloes Benjamín Iñíguez Article IETE Journal of Research 2012 58(3):197-204doi:10.4103/0377-2063.97326 IETE Journal of Research 10.4103/0377-2063.97326 http://www.jr.ietejournals.org/text.asp?2012/58/3/197/97326 http://www.jr.ietejournals.org/text.asp?2012/58/3/197/97326583 197 204 http://www.jr.ietejournals.org/text.asp?2012/58/3/197/97326 Mike Schwarz, Thomas Holtij, Alexander Kloes, Benjamín Iñíguez

IETE Journal of Research 2012 58(3):197-204

A new technique to calculate the channel electric field in Double-gate MOSFETs and Schottky barrier Double-gate MOSFETs (SB-DG-MOSFETs) in sub-threshold region is presented. 2D Poisson΄s equation is solved in an analytical closed form with the conformal mapping technique. The estimated solution of the two-dimensional electric field with its complex components is analyzed with the bias conditions for accumulation and inversion regions, which have been applied and studied in detail. A comparison with data simulated by 2D TCAD Sentaurus simulator for channel lengths down to 22 nm was made and is in a good agreement to this simulation results.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/197/97326 Thomas Holtij Mike Schwarz Alexander Kloes Benjamín Iñíguez Article IETE Journal of Research 2012 58(3):205-213doi:10.4103/0377-2063.97328 IETE Journal of Research 10.4103/0377-2063.97328 http://www.jr.ietejournals.org/text.asp?2012/58/3/205/97328 http://www.jr.ietejournals.org/text.asp?2012/58/3/205/97328583 205 213 http://www.jr.ietejournals.org/text.asp?2012/58/3/205/97328 Thomas Holtij, Mike Schwarz, Alexander Kloes, Benjamín Iñíguez

IETE Journal of Research 2012 58(3):205-213

In this work, we investigate the impact of the parasitic resistances in the contiguous zones of the Double-gate MOSFET (DG-MOSFET). Since the channel length is scaled down to 20 nm, the parasitic source/drain resistances get more important and cannot be neglected. To calculate these resistances in such devices, a two-dimensional model in analytical closed form has been derived by using the conformal mapping technique. The model is able to predict the parasitic resistances for DG-MOSFETs as well as for devices with raised source drain (RSD) structures and/or wrapped contacts. The influence of source/drain geometries on the access resistances is accurately described. A bias dependency is obtained by introducing a field-dependent approach. At last, the results from the model are compared with the parasitic source/drain resistances determined from TCAD device simulation software.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/205/97328 Antonios Bazigos François Krummenacher Jean-Michel Sallese Matthias Bucher Ehrenfried Seebacher Werner Posch Kund Molnár Mingchun Tang Article IETE Journal of Research 2012 58(3):214-221doi:10.4103/0377-2063.97329 IETE Journal of Research 10.4103/0377-2063.97329 http://www.jr.ietejournals.org/text.asp?2012/58/3/214/97329 http://www.jr.ietejournals.org/text.asp?2012/58/3/214/97329583 214 221 http://www.jr.ietejournals.org/text.asp?2012/58/3/214/97329 Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang

IETE Journal of Research 2012 58(3):214-221

The High-Voltage MOSFET is used in a wide variety of applications covering from power systems up to RF-IC. Compact models that describe the high-frequency behavior of the device are required to predict high-frequency operation and switching capabilities of these elements in HV state-of-the-art systems. In this paper, an RF model is presented and verified against extensive Y-parameter measurements, which were carried out on a long channel Lateral double-Diffusion MOS device. Assessment of the model with measurements confirms the validity of this approach.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/214/97329 Petr Beták Petr Zavrel Article IETE Journal of Research 2012 58(3):222-225doi:10.4103/0377-2063.97330 IETE Journal of Research 10.4103/0377-2063.97330 http://www.jr.ietejournals.org/text.asp?2012/58/3/222/97330 http://www.jr.ietejournals.org/text.asp?2012/58/3/222/97330583 222 225 http://www.jr.ietejournals.org/text.asp?2012/58/3/222/97330 Petr Beták, Petr Zavrel

IETE Journal of Research 2012 58(3):222-225

One specific modeling challenge is model conversion between SPECTRE and HSPICE simulator syntaxes. The SPECTRE simulator uses a standard model of the physical resistor. Our approach introduces a methodology to create an HSPICE-based model of physical resistor which uses the same set of parameter values as a SPECTRE model. A physical resistor consists of a simple resistor and two junction diodes that are reverse biased during normal operation. The comparison between SPECTRE and HSPICE simulation results is included.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/222/97330 Lenka Sochová Petr Beták Ján Plojhár Article IETE Journal of Research 2012 58(3):226-229doi:10.4103/0377-2063.97332 IETE Journal of Research 10.4103/0377-2063.97332 http://www.jr.ietejournals.org/text.asp?2012/58/3/226/97332 http://www.jr.ietejournals.org/text.asp?2012/58/3/226/97332583 226 229 http://www.jr.ietejournals.org/text.asp?2012/58/3/226/97332 Lenka Sochová, Petr Beták, Ján Plojhár

IETE Journal of Research 2012 58(3):226-229

This paper deals with enhancement of a PN diode standard model toward including substrate PN junction, and reverse recovery effect models. This leads to improvement in power management, EMC, and switching application design.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/226/97332 Risho Koh Takahiro Iizuka Article IETE Journal of Research 2012 58(3):230-236doi:10.4103/0377-2063.97331 IETE Journal of Research 10.4103/0377-2063.97331 http://www.jr.ietejournals.org/text.asp?2012/58/3/230/97331 http://www.jr.ietejournals.org/text.asp?2012/58/3/230/97331583 230 236 http://www.jr.ietejournals.org/text.asp?2012/58/3/230/97331 Risho Koh, Takahiro Iizuka

IETE Journal of Research 2012 58(3):230-236

For the use of circuit simulation model for power Metal-Oxide-Silicon Field Effect Transistors (MOSFETs), the extraction of self-heating parameters based on transient I-V measurements has been developed. A set of transient drain current was measured through a pulsed I-V setup. The thermal resistance and thermal capacitance are extracted from the set of transient current data. The self-heating-free drain current, which is required for MOSFET model extraction, is obtained by extrapolating the transient data to t=0. Since the measurements after a certain delay are analyzed in this method, a very short pulse measurement which tends to suffer from ringing noises and requires a complicated DUT design is not required. The accuracy of the method is demonstrated for a power MOS model using the BSIMSOI parameter set.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/230/97331 Lorenzo Labate Simona Angela Cozzi Roberto Stella Article IETE Journal of Research 2012 58(3):237-242doi:10.4103/0377-2063.97333 IETE Journal of Research 10.4103/0377-2063.97333 http://www.jr.ietejournals.org/text.asp?2012/58/3/237/97333 http://www.jr.ietejournals.org/text.asp?2012/58/3/237/97333583 237 242 http://www.jr.ietejournals.org/text.asp?2012/58/3/237/97333 Lorenzo Labate, Simona Angela Cozzi, Roberto Stella

IETE Journal of Research 2012 58(3):237-242

Many applications affecting our daily life require devices that can reach very high voltages. These applications are generally controlled by a logic shifted up to, for example, 600 V with respect to the ground. The device adopted in order to let high-voltage world talk with low-voltage logic is a level shifter, here nicknamed "Mickey Mouse" due to its particular shape. Since it can be composed by several elements, such as linear, curved, and ball-shaped transistors (ears of "Mickey Mouse"), the model has to take into account the scalability of the device in terms of linear width, number of curves, and number of ears. Extraction strategy and methodology used to achieve an accurate model will be presented in this work.]]> Sat,16 Jun 2012http://www.jr.ietejournals.org/text.asp?2012/58/3/237/97333