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Conventional modeling and simulation of two-phase switched current MOS-integrated circuits is normally undertaken at semiconductor device level. This allows primary and secondary circuit effects to be studied and characterized. However, with the growing complexity of these circuits, transient domain simulation times can become prohibitively long, restricting the size of circuit that can be easily investigated. Measurable reductions in transient simulation run times can be achieved by modeling part, or all, of a switched current design as a macromodel. This paper introduces a hybrid approach to MOS switched current circuit modeling that combines the primary features of compact device modeling with functional circuit macromodeling. To illustrate the proposed hybrid modeling procedure the properties, and simulation model, of a MOS switched current analog memory cell are described. The material presented also demonstrates how recent trends in "Quite universal circuit simulator" (QUCS) technology promote embedded Verilog-A models and equation-defined subcircuits as integral elements in mixed-mode circuit and system design.

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In this work, we investigate the impact of the parasitic resistances in the contiguous zones of the Double-gate MOSFET (DG-MOSFET). Since the channel length is scaled down to 20 nm, the parasitic source/drain resistances get more important and cannot be neglected. To calculate these resistances in such devices, a two-dimensional model in analytical closed form has been derived by using the conformal mapping technique. The model is able to predict the parasitic resistances for DG-MOSFETs as well as for devices with raised source drain (RSD) structures and/or wrapped contacts. The influence of source/drain geometries on the access resistances is accurately described. A bias dependency is obtained by introducing a field-dependent approach. At last, the results from the model are compared with the parasitic source/drain resistances determined from TCAD device simulation software.

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A new technique to calculate the channel electric field in Double-gate MOSFETs and Schottky barrier Double-gate MOSFETs (SB-DG-MOSFETs) in sub-threshold region is presented. 2D Poisson΄s equation is solved in an analytical closed form with the conformal mapping technique. The estimated solution of the two-dimensional electric field with its complex components is analyzed with the bias conditions for accumulation and inversion regions, which have been applied and studied in detail. A comparison with data simulated by 2D TCAD Sentaurus simulator for channel lengths down to 22 nm was made and is in a good agreement to this simulation results.

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Many applications affecting our daily life require devices that can reach very high voltages. These applications are generally controlled by a logic shifted up to, for example, 600 V with respect to the ground. The device adopted in order to let high-voltage world talk with low-voltage logic is a level shifter, here nicknamed "Mickey Mouse" due to its particular shape. Since it can be composed by several elements, such as linear, curved, and ball-shaped transistors (ears of "Mickey Mouse"), the model has to take into account the scalability of the device in terms of linear width, number of curves, and number of ears. Extraction strategy and methodology used to achieve an accurate model will be presented in this work.

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The High-Voltage MOSFET is used in a wide variety of applications covering from power systems up to RF-IC. Compact models that describe the high-frequency behavior of the device are required to predict high-frequency operation and switching capabilities of these elements in HV state-of-the-art systems. In this paper, an RF model is presented and verified against extensive Y-parameter measurements, which were carried out on a long channel Lateral double-Diffusion MOS device. Assessment of the model with measurements confirms the validity of this approach.

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Usually, aging models implemented in design kits are able to accurately describe parameter degradation only if kinetics during constant voltage stress is relatively simple; a methodology is proposed to extend aging simulation to a more complex behavior, and indeed implementable into a commercial software environment (in the case Eldo UDRM by Mentor Graphics). The methodology is applied to describe Ron drift of a 40 V Nch MOS transistor.

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For the use of circuit simulation model for power Metal-Oxide-Silicon Field Effect Transistors (MOSFETs), the extraction of self-heating parameters based on transient I-V measurements has been developed. A set of transient drain current was measured through a pulsed I-V setup. The thermal resistance and thermal capacitance are extracted from the set of transient current data. The self-heating-free drain current, which is required for MOSFET model extraction, is obtained by extrapolating the transient data to t=0. Since the measurements after a certain delay are analyzed in this method, a very short pulse measurement which tends to suffer from ringing noises and requires a complicated DUT design is not required. The accuracy of the method is demonstrated for a power MOS model using the BSIMSOI parameter set.

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This paper deals with enhancement of a PN diode standard model toward including substrate PN junction, and reverse recovery effect models. This leads to improvement in power management, EMC, and switching application design.

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One specific modeling challenge is model conversion between SPECTRE and HSPICE simulator syntaxes. The SPECTRE simulator uses a standard model of the physical resistor. Our approach introduces a methodology to create an HSPICE-based model of physical resistor which uses the same set of parameter values as a SPECTRE model. A physical resistor consists of a simple resistor and two junction diodes that are reverse biased during normal operation. The comparison between SPECTRE and HSPICE simulation results is included.

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